Random access memory (RAM) is a component used within electronic systems to store data for use by other components within the system. Dynamic RAM (DRAM) is a type of RAM which uses a capacitor-type storage and requires periodic refreshing in order to maintain the data stored within the DRAM. Static RAM (SRAM) is another type of RAM which retains the information stored within the SRAM as long as power is applied. SRAM does not require periodic refreshing in order to maintain the stored data.
RAM is generally organized within the system into addressable blocks, each containing a predetermined number of memory cells. Each memory cell within a RAM represents a bit of information. The memory cells are organized into rows and columns. Each row of memory cells forms a word. Each memory cell within a row is coupled to the same wordline which is used to activate the memory cells within the row. The memory cells within each column of a block of memory are also each coupled to a pair of bitlines. These bitlines are also coupled to local input/output (LIO) lines. These local input/output lines are used to read data from an activated memory array or write data to an activated memory array. The pair of bitlines includes a bitline and an inverse bitline. A memory cell is therefore accessed by activating the appropriate wordline and pair of bitlines.
Synchronous DRAM (SDRAM) operates within a synchronous memory system such that input and output signals are synchronized to an active edge of a system clock. Most SDRAMs are capable of synchronously providing burst data in a burst mode at a high-speed data rate by automatically generating a column address for storing data within and retrieving data from the SDRAM. Any data within this write burst sequence can be masked by the system so that it is not written into the device. The masking function is typically controlled by a mask control signal which is usually provided to the SDRAM through a dedicated pin.
Generally, before a memory access operation is performed to or from a memory cell within a block of memory, the pairs of bitlines or LIO signal lines within that block of memory are all precharged to a specified voltage level. A memory access operation includes both write and read operations. The precharge operation equalizes the voltage level of the bitlines at a known level, to enhance reliability of the data written to a cell and to allow quick detection of data read from a cell. Because the same pair of LIO signal lines is used for all memory cells within a column, if the bitlines are not precharged or equalized before each memory operation, then a second access to a memory cell within the column would require that the LIO signal lines are first equalized from their previous voltage level to a known voltage level and then brought to the appropriate logical voltage level. Accordingly, in order to speed up the performance of the memory, the LIO signal lines within a block of memory are typically all precharged to the specified known voltage level after each memory operation, in anticipation of the next memory operation. This allows the LIO signal lines to be reliably brought to the appropriate logical voltage level faster during the memory operation.
Relevant portions of an SDRAM circuit which implement an equalization and precharge circuit for a pair of LIO signal lines in a conventional manner are illustrated in FIG. 1. This equalization and precharge circuit includes three transistors M1, M2 and M3. The drains of the transistors M1 and M2 are both coupled to the supply voltage VCC. The source of the transistor M1 is coupled to the drain of the transistor M3 and to the signal line LIO. The source of the transistor M2 is coupled to the source of the transistor M3 and to the signal line LIO.sub.--. The gates of the transistors M1, M2 and M3 are all coupled together and to an equalization control signal line LIOEQ. In this memory circuit, the equalization control signal line LIOEQ is at a logical high voltage level during standby cycles and during precharge cycles between memory access operations. At all other times, the equalization control signal line LIOEQ is at a logical low voltage level.
During read and write operations, the signal line LIO carries a logical value representing the data read from or to be written to the addressed memory cell. During read and write operations, the signal line LIO.sub.-- carries a logical value representing the inverse of the data on the signal line LIO. The signal lines LIO and LIO.sub.-- are coupled to a data amplifier 10 and to a sense amplifier array 12. The sense amplifier 12 is coupled to bitlines Bitn and Bitn.sub.--. The bitline Bitn.sub.-- carries a logical value representing the inverse of the data on the bitline Bitn. During a read operation, the data from the addressed memory cell is latched into the sense amplifier 12. This latched data is also represented on the signal lines LIO and LIO.sub.--. The data amplifier 10 then amplifies the change in the signal lines LIO and LIO.sub.-- during a read operation, from the precharge level to a level representing the data being read from the addressed memory cell. In the case of a write operation, the sense amplifier 12 determines the appropriate sense of the data on the signal lines LIO and LIO.sub.--, during the write operation and transmits this data to the bitlines Bitn and Bitn.sub.-- of the selected sense amplifier.
Timing diagrams illustrating the operation of the equalization and precharge circuit of FIG. 1 are illustrated in FIG. 2. Waveforms representing the values of the signal lines LIO and LIO.sub.-- are illustrated in FIG. 2A. A waveform representing the value of the equalization control signal line LIOEQ is illustrated in FIG. 2B. As shown in FIG. 2B, the equalization control signal line LIOEQ is at a logical high voltage level during the initial standby cycle. During this standby cycle, when the equalization control signal line LIOEQ is at a logical high voltage level, the transistors M1, M2 and M3 are all turned on and the signal lines LIO and LIO.sub.-- are both precharged to a voltage level equal to the level of the supply voltage VCC less the transistor threshold voltage VT.
During the first and subsequent memory access operations, the value of the signal lines LIO and LIO.sub.-- then diverge from the precharged level, based on the data being read from or written to the addressed memory cell during the memory operation. After the first and subsequent memory access operations, the equalization control signal line LIOEQ is then raised to a logical high voltage level to turn on the transistors M1, M2 and M3 and precharge and equalize the values of the signal lines LIO and LIO.sub.-- before the next memory access operation. However, as illustrated in FIG. 2, during a typical precharge operation in a high-speed memory, the precharge cycle is not of a duration that is long enough to precharge the values of the signal lines LIO and LIO.sub.-- to a level equal to VCC-VT. As illustrated in FIG. 2A, because of the limited duration of the precharge cycle in high-speed memory devices, the precharged level of the signal lines LIO and LIO.sub.-- will degrade over time from the initial level of VCC-VT. This degradation can cause problems in the operation of the data amplifier 10, which is typically optimized to operate within a limited range of voltage levels. Operating outside of this optimal range will cause delays in the operation of the data amplifier 10.
As also illustrated in FIG. 2A, after the first few memory access operations, due to the limited duration of the precharge cycles, the signal lines LIO and LIO.sub.-- are not fully equalized before each memory access operation. This equalization level does not become acceptable until the precharge level of the signals LIO and LIO.sub.-- degrades to a level approaching half of the supply voltage VCC. Once the precharge level degrades to this level, the equalization and precharge circuit, as illustrated in FIG. 1, is able to equalize the signal lines LIO and LIO.sub.-- to this level during the precharge cycles. However, the non-equalization of the signal lines LIO and LIO.sub.-- during the early precharge cycles can cause functionality problems during the early memory access operations.